Coal Creek is skilled in Verilog and VHDL for synthesis, including SOC design flow and timing closure. Our FPGA skills include verification using System Verilog for mixed language designs using VHDL. Past projects have included the following:
- Microblaze based servo SOC development
- System architecture
- Microblaze instantiation
- Servo bring-up and test
- Development of sample C code to provide a head start for software team
- Development of working UBoot code on Altera NIOS2 processor
- Spartan 6 Verilog project to support many additional communication lanes for a FreeScale i.MX6 processor
- System Verilog test bench and verification environment for a aerospace project
- Verilog designs of SPI communication – based CPLD for medical product and oil exploration system
- PCB board timing analysis
